1. Field of the Invention
The present invention relates to a programmable frequency dividing apparatus, and more specifically to a programmable frequency dividing apparatus which is suitable for use in a slip phase control phase-locked loop or the like and comprises a plurality of stages of cascade-connected programmable frequency dividers each of which is capable of selecting either one of variable division ratios of two and three so as to divide the frequency of an input signal by the division ratio thus selected.
There has not heretofore been proposed a programmable frequency dividing apparatus comprising a 2-scale-factor prescaler arranged in the form of plural stages in tandem, of such a type that the division of the frequency of an input signal by two and three is carried out. However, one example of the programmable frequency dividing apparatus has been proposed by the present applicant. As shown in FIG. 1, the proposed programmable frequency dividing apparatus has an inverter circuit 1, OR gates 2, 6, 8, a NOR gate 4, D flip-flop (D-FF) circuits 5, 7, and a buffer amplifier 3. As illustrated in FIG. 2, a programmable frequency divider 9 capable of selecting either one of variable division ratios of two and three in response to a preset input Di (Di is equal to either a logic "1" level or a logic "0" level) at each terminal D of the programmable frequency divider 9 is cascade-connected in the form of plural stages, thereby obtaining a desired division ratio. FIG. 2 shows one example in which programmable frequency dividers 9-0, 9-1, 9-2, . . . are cascade-connected to one another.
In the above programmable frequency divider 9, when an input signal at a terminal MOD is of a logic "1" level, a signal of the logic "1" level is delivered (outputted) to a terminal OC. Then, a clock signal inputted to a terminal CP is frequency-divided by two on the positive edge of the clock signal and the result of its frequency division is delivered to a terminal Q.
On the other hand, when the input signal at the MOD terminal is of a logic "0" level, a signal of the same level as that at the Q terminal is supplied to the OC terminal. When an input signal at a D terminal is of a logic "1" level, the input clock signal at the CP terminal is frequency-divided by three on the positive edge thereof and the result of its frequency division is sent to the Q terminal. Further, when the input signal at the D terminal is of a logic "0" level, the input clock signal at the CP terminal is frequency-divided by two on the positive edge thereof and the result of its frequency division is delivered to the Q terminal.
With the above arrangement of the type wherein the programmable frequency divider 9 has been arranged in tandem in the form of plural stages, an nth programmable frequency divider divides the frequency of the clock pulse signal by 2+D (D=0 or 1, which is determined depending on the level of a code supplied to the terminal D) only once in response to the level of the input signal at the D terminal when the outputs at the respective terminals Q of the programmable frequency dividers subsequent to the nth programmable frequency divider are all zero, followed by the division of the frequency of the clock pulse signal by two.
A description will now be made of the programmable frequency dividers 9 cascade-connected in the form of three stages, for example, in which a terminal MOD.sub.2 of a programmable frequency divider (9-2) corresponding to a third stage is connected to the earth and set to a logic "0" level.
An input signal at the terminal MOD.sub.2 is of a logic "0" level at all times. When a terminal D.sub.2 (a signal applied to the terminal D.sub.2) is of a logic "0" level, a CP.sub.2 signal is frequency-divided by two. Further, when the D.sub.2 terminal is maintained at a logic "1" level, the CP.sub.2 signal is frequency-divided by three. In other words, the programmable frequency divider as the third stage divides the frequency of the input signal by 2+D.sub.2 (D.sub.2 =0 or 1, which is determined depending on the level of a code supplied to the terminal D.sub.2).
In order to deliver 2+D.sub.2 clock signals as frequency-divided outputs to a terminal Q.sub.1, a programmable frequency divider 9 1 as a second stage firstly divides the frequency of the input signal by 2+D.sub.1 (D.sub.1 =0 or 1, which is determined depending on the level of a code supplied to a terminal D.sub.1) one time. This divider then divides the frequency of the signal by the remaining 1+D.sub.2, i.e., by two. That is to say, the programmable frequency divider 9-1 as the second stage and the programmable frequency divider 9-2 as the third stage respectively divide the frequencies of the CP.sub.1 and CP.sub.2 signals by division ratio setting codes (numbers) determined by the following equation (1): ##EQU1##
Similarly, in order to deliver (2+D.sub.2).times.2+D.sub.1 clock signals to the output of a programmable frequency divider 9-0 as a first stage, pulses of a CP.sub.0 signal according to a division ratio setting code (number) represented by the following equation (2) are counted: EQU [(2+D.sub.2).times.2+D.sub.1 ].times.2+D.sub.0 =2.sup.3 +D.sub.2 .times.2.sup.2 +D.sub.1 .times.2.sup.1 +D.sub.0 .times.2.sup.0 ( 2)
Thus, the total output as a frequency-divided output can be determined from the programmable frequency divider 9-2 by dividing the frequency of the CP.sub.0 signal by a division ratio determined from the following equation (3): EQU 2.sup.3 +D.sub.2 .times.2.sup.2 +D.sub.1 .times.2.sup.1 +D.sub.0 .times.2.sup.0 ( 3)
In the same manner as described above, the programmable frequency dividing apparatus comprising the programmable frequency divider 9 arranged in the form of n stages in tandem divides the input frequency by the division ratios determined by the following equation (4): EQU 2.sup.n +D.sub.n-1 .times.s.sup.n-1 +. . . +D.sub.2 .times.2.sup.2 +D.sub.1 .times.2.sup.1 +D.sub.0 .times.2.sup.0 ( 4)
The input signal is frequency divided by a continuously variable division ratio represented by the following equation (5): EQU 2.sub.2.about. 2.sup.n+1 -1 (5)
However, when an instruction signal (hereinafter called "(+1) instruction signal ") for incrementing the division ratio by "+1" is inputted, the input signal cannot be frequency-divided by the division ratio greater than a preset division ratio by "+1".
Therefore, there has been proposed the following arrangement in order to cause a programmable frequency divider to divide an input frequency by a division ratio greater than a preset division ratio by "+1" in the PLL, for example. Specifically, let's now assume that a preset value of the programmable frequency divider is of an N bit. Under this condition, an N-bit adder is provided so that it is supplied with a "+1" instruction signal, thereby enabling the programmable frequency divider to divide the input frequency by the division ratio greater than the preset division ratio by "+1".
With the above arrangement, however, the N-bit adder is required. Therefore, the above arrangement develops problems such as increased circuit scales and an increased number of signal processing cycles, thereby making a circuit arrangement complex.